1. Field of the Invention
The invention relates to a semiconductor device and a fabrication method thereof. More particularly, the invention relates to an interconnection structure and a fabrication method thereof, which are characterized by an ability to reduce stress.
2. Description of the Related Art
As the line width of the semiconductor device keeps reducing to achieve a higher integration, the resistance of the interconnection in the device becomes higher, and a parasitic capacitance that occurs between the conductive lines also becomes more significant. This would reduce the operation speed of the device due to the well-known RC delay. So, Copper (Cu) with a low resistance, as well as low dielectric constant (low-k) materials having a dielectric constant lower than that of silicon oxide become necessary choices of materials in the manufacture process. And among different low-k materials, organic low-k material is one type that is most commonly known.
However, since the organic low-k material has characteristics that differ significantly from those of the inorganic materials commonly adopted in the device. For instance, the heat expansion coefficient of the organic low-k material is several times larger than the inorganic material. So, large amount of stress is often produced due to the temperature variation. For example, during the in-line process, thermal cycling, or stress migration test that requires a high temperature and long duration, the via that forms in the organic low-k material layer is often deformed due to a very large stress. And when the via is deformed, it is possible to cause degradation of the via resistance (i.e. increased resistance), and even to create an open circuit.
FIG. 1 is a schematic diagram illustrating a conventional dual damascene structure having a via therein. As shown in FIG. 1, a substrate 100 is provided with a copper layer 110 already formed therein. A cap layer 120 made of silicon nitride and an organic low-k material layer 130 are formed in sequence on the substrate 100. The organic low-k material layer 130 has therein a via opening 140 that penetrates the cap layer 120 and a trench 150 above the via opening 140. Furthermore, a diffusion barrier layer 160 that serves to prevent diffusion of the metal atoms is formed to cover a surface of the via opening 140 and the trench 150. The via opening 140 and the trench 150 are then filled with a metal to form a via 170 and a conductive line 180.
Referring to table 1 provided below, illustrating stress results obtained from simulating the dual damascene structure according to one preferred embodiment using commercial software “Tsupreme”. Referring to FIG. 1, a direction that is parallel to a surface of the substrate 100 is set to be x direction, while a direction that is vertical to the surface of the substrate 100 is set to be y direction. And a stress from x direction Sxx, a stress from y direction Syy, and a shearing stress from xy plane Sxy are simulated results to be obtained. Except of three variations in the sidewall tilted angles θ of the via opening 140, parameters for the other parts of the dual damascene structure are similar to those in the prior art.
As shown in the simulated results, the stresses mainly accumulate at a junction 190 (circled by a dotted line) between the organic low-k material layer 130 and a portion of the capping layer adjacent to the via 170.
TABLE 1Tilted angle ofStress (J/cm2)sidewall θSyySxxSxy8855.452.838.38061.544.131.37561.332.123.5
As shown in table 1, the via 170 is subjected mainly to the stresses Sxx and Syy from x and y directions, particularly the stress Syy, while the shearing stress Sxy is the minimal. On the other hand, after inspecting a batch of the failed devices, it is found that there are many damaged via as well as occurrence of delamination at a junction between the diffusion barrier layer 160-copper layer 110 caused by an oversized stress Syy. The damaged via would make the device ineffective, while the delamination that occurs between the diffusion barrier layer 160-copper layer 110 would cause a high leakage current.
So, in order to solve the problem of degrading the via when subjected to a thermal process, the stress Syy needs to be reduced without increasing the stresses from other directions for preventing other problems to occur. However, as seen in the simulated results in table 1, the stress Sxx varies inversely with the stress Syy in the prior art. That is, as the tilted angle θ increases, the stress Syy may be reduced slightly, but the stress Sxx would be increased significantly. Thus, to prevent other problems caused by an oversized stress Sxx, the room for adjusting the stress Syy becomes limited.